The present invention relates to a logic circuit which operates at high speed even with a large load capacitance in an LSI and can be optimally designed in accordance with various required conditions, e.g., the load capacitance, the power consumption, and the size of each of the elements required to constitute a logic circuit, such as transistors, capacitors, resistors.
When an LSI is to be constituted by an ultra-high-speed logic circuit, in order to increase the speed of a conventional ECL circuit, a circuit which allows an increase in speed with a small increase in power consumption is known, as disclosed in Kai-Yap Toh et al., "A 23-ps/2.1-mW ECL Gate With an AC-Coupled Active Pull-Down Emitter-Follower Stage", IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989, pp. 1301-1306. As described in this literature, such a circuit is realized by increasing a current flowing through an emitter-follower stage only when an output signal goes from high level to low level.
FIG. 2 is a circuit diagram of a conventional logic circuit. Referring to FIG. 2, the conventional logic circuit comprises: an input signal source 201; transistors 211 and 212 whose bases are respectively connected to the first and second outputs of the input signal source 201; a constant current source 202 having a first terminal connected to the emitters of the transistors 211 and 212, and a second terminal connected to a power source VEE; resistors 221 and 222 having first terminals connected to GND, and second terminals respectively connected to the collectors of the transistors 211 and 212; a transistor 215 having a collector and a base respectively connected to GND and the collector of the transistor 212; resistor 226 having a first terminal connected to the emitter of the transistor 215 and a second terminal connected to a power source VTT; a capacitor 230 having a first terminal connected to the collector of the transistor 211; a transistor 216 having a collector connected to the emitter of the transistor 215, a base connected to the second terminal of the capacitor 230, and an emitter connected to the power source VTT; a transistor 214 having a collector and a base respectively connected to GND and a reference voltage Vref; and a resistor 225 having a first terminal connected to the emitter of the transistor 214, and a second terminal connected to the power source VTT.
FIGS. 3A to 3E are timing charts showing operating states of the circuit shown in FIG. 2.
An operation of the conventional logic circuit shown in FIG. 2 will be described with reference to FIG. 3. Assume that the waveform shown in FIG. 3A, which changes from high to low, is supplied from the input power source 201 to the base of the transistor 211. In this case, the differential outputs shown in FIGS. 3B and 3C are obtained from the collectors of the transistors 212 and 211, respectively. The positive-phase output shown in FIG. 3B, obtained from the transistor 212, serves to drive an emitter-follower circuit constituted by the transistor 215 and the resistor 226.
The negative-phase output shown in FIG. 3C, obtained from the transistor 211, is differentiated by the capacitor 230 to be formed into a waveform having a peak at the trailing edge of the input waveform, as shown in FIG. 3D, thus driving the transistor 216 for a period of time corresponding to a given time constant. Consequently, as shown in FIG. 3E, a current having a peak at the trailing edge of the output flows through the emitter of the transistor 216 to cause a load capacitance 240 to quickly discharge.
Additionally, when the bias voltage Vref, that is applied to an emitter-follower circuit constituted by the transistor 214 and the resistor 225, determines a bias current flowing through the emitter of the transistor 216. By adjusting the bias voltage Vref, the amount of current to be discharged through the transistor 216 is determined.
In this manner, the logic circuit shown in FIG. 2 operates as a buffer for directly transferring an input logic signal.
In an ECL (emitter-coupled logic) circuit whose output stage is constituted by only an emitter-follower circuit, the discharge of the load capacitance 240 at the trailing edge of the output is performed through only the resistor 226. For this reason, if the resistance of the resistor 226 is increased to reduce the power consumption, the delay at the trailing edge of the output is increased. However, by using the circuit shown in FIG. 2, the delay can be reduced without increasing the power consumption.
In the above-described conventional logic circuit, the delay can be reduced at the trailing edge of the output. However, since the differentiating capacitor 230 is directly connected to the collector of the transistor 211 constituting a current switch, the delay of the current switch is increased at the leading edge of the current switch output.
In addition, although the bias current of the transistor 216 is determined by the bias voltage Vref, since this bias current Ib and the bias voltage Vref have the following relationship: EQU Ib=Io[exp{(qVref)/(kT)}-1]
a slight change in Vref causes a great change in the bias current Ib. This greatly changes the delay characteristics of the logic circuit.
Similarly, a temperature change causes a change in built-in base-emitter voltage Vf in the transistors 214 and 216, and consequently a great change in the bias current Ib.
Furthermore, in the conventional logic circuit, there has been no method of optimizing the driving performance with respect to a load capacitance.